![]() ![]() The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The material characterization was locally performed at different points by high resolution transmission electron microscopy, while it was globally performed by high resolution X-ray diffraction and photoluminescence.Īt the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). Tensile strain appears in the first global Ge layer, compressive strain in the single-step Ge layer and fully strain relaxation in the dual-step Ge layer. The strain has also been modulated along the cross-section of the sample. The final root mean square (RMS) of the surface roughness was 0.64 nm. This means that by introducing a single SEG step, the defect density could be reduced by two orders of magnitude, but this reduction could be further decreased by only 11.3% by introducing the second SEG step. With the single-step SEG of Ge, the threading defect density (TDD) was successfully decreased from 2.9 × 107 cm−2 in a globally grown Ge layer to 3.2 × 105 cm−2 for a single-step SEG and to 2.84 × 105 cm−2 for the dual-step SEG of the Ge layer. In this manuscript, a novel dual-step selective epitaxy growth (SEG) of Ge was proposed to significantly decrease the defect density and to create fully strained relaxed Ge on a Si substrate. Hence, the predictive TCAD simulations explored the new avenues of strain-engineered FinFET for future CMOS technology generations. These results predict the improvement of the drive current and reduction in short channel effect with the appropriate selection of the θ Fin and θ Epi. The variation of electrical performances with change in epi angle (θ Epi ) and fin angle (θ Fin ) is critically analyzed. A process induced compressively stressed p-channel FinFET at 7nm Technology node is virtually fabricated using Technology CAD (TCAD) by introducing a SiGe epitaxial layer at Source and Drain regions. The variation of two design parameters (fin angle and epi angle) can lead to a change in stress and hence the devices’ electrical performance, which is the major focus of this study. This work proposes an improvement of electrical performance through process induced stress optimization for a compressively stressed FinFET at a 7nm Technology node. Their optimal design and improved performance are key demands for most of the leading semiconductor manufacturing industries. At 7nm technology node, the trigate FinFETs are the promising candidates for modern integrated circuits. ![]()
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